Introduction of Laser Pi-Grooving as Breakthrough Solution to Enhance die Strength of 40 nm ulow-k CMOS Silicon Technology during Wafer Saw Process

Nowadays, semiconductors and electronics are becoming part of our everyday activities. As the Integrated circuits become more useful to people, it also requires more function, which contain more complex and compact components. Aligned to this package requirement, the more challenging it become to package development as Silicon technology becomes more critical and complex from bare silicon to conventional MOS technology to Ultra Low-K, which requires a different strategy. The new process development in the Semiconductor industry is a necessity to cope up with these new technologies. Low-k devices always pose a big challenge in achieving good dicing quality. This is because of the weak mechanical properties of the low-k dielectric material used. Mechanical Sawing is the most popular cutting method for silicon, but with Ultra low-K technology, using mechanical sawing will lead to various sawing defects such as chippings and delamination [1,2]. These leads to the introduction of Laser Grooving to get rid of these dilemmas. Laser grooving uses heat to eradicate metals on this very thin metal wafer dicing saw streets in preparation for wafer saw process to prevent topside chippings and delamination/metal peel off [3]. These defects are not acceptable especially since the product application is a chip card. Since chip cards must be flexible and durable, they require higher die and package strength to serve its purpose. To achieve such package requirement, different method was evaluated such as standard mechanical dicing, standard Laser Grooving and the PI laser groove.

The paper will discuss how we were able to achieve the quality requirement for Ultra Low-K and at the same time eliminating top reject contributor during startup of this device.